　　Today, the majority of electronic circuits (including microprocessors, microcontrollers,FPGAs, and CPLDs) are based on clocked logic, requiring a timing source. Depending on the frequency accuracy requirements, some employ oscillators while others use off-the-shelf quartz crystals in conjunction with the builtin oscillator circuit embedded in most microcontrollers and microprocessors.
　　Most if not all embedded solutions use the Pierce oscillator configuration,integrated as part of the SoC (systemon-chip). The obvious advantages include cost, size, and power compared to a standalone oscillator. The key limitation is the proper matching of the quartz crystal with the on-board Pierce oscillator.
　　Figure 1 outlines the oscillator block and the key components that influence the overall performance of the timing loop. Let the effective load capacitance, as seen by the crystal, be CL.
　　如今,大多數電子電路（包括微處理器,微控制器,FPGA和CPLD）都基于時鐘邏輯,需要定時源. 根據頻率精度要求,一些采用振蕩器,而另一些采用現成的石英晶體與嵌入大多數微控制器和微處理器的內置振蕩器電路相結合.
　　大多數（如果不是全部）嵌入式解決方案都使用皮爾斯振蕩器配置,作為SoC（systemon-chip）的一部分集成. 與獨立振蕩器相比,明顯的優勢包括成本,尺寸和功耗. 關鍵的限制是石英晶振與板載皮爾斯振蕩器的正確匹配.
圖1概述了振蕩器模塊和影響定時環路整體性能的關鍵組件. 讓晶體看到的有效負載電容為CL.

For example, let C1 = C2 = 27 pF; CIN = 5.0 pF and COUT = 10.0 pF and Board Strays = 0.50 pF.
例如,設C1 = C2 = 27 pF; CIN = 5.0pF,COUT = 10.0pF,板間距= 0.50pF.

　　Therefore specifying a crystal with 18.0 pF plating load capacitance would be the closest match for frequency accuracy. The selected capacitors primarily influence the overall oscillator loop capacitance, as seen by the crystal. This effective loop capacitance (CL from Eq. 1) determines how far the oscillator loop is resonating, relative to the desired resonant frequency. However, the overall longterm performance of the oscillator loop is influenced by the following factors:
　　因此,指定具有18.0 pF電鍍負載電容的晶體將是頻率精度最接近的匹配. 所選擇的電容主要影響整個振蕩器環路電容,如晶體所示. 該有效環路電容（來自等式1的CL）確定振蕩器環路相對于所需諧振頻率諧振的程度. 但是,振蕩器環路的整體長期性能受以下因素影響：
• The reactive impedance (Xc) of these loop capacitors.
• The inverter amplifier’s transconductance (gm).
• The presence or absence of the current limiting resistor (Rs).
• The presence or absence of the automatic gain control (AGC) or automatic level control (ALC); with-in the integrated oscillator circuit.
These factors collectively set the boundary condition of the design. This boundary condition, commonly referred to as the safety factor (SF), is an important parameter to ensure that the product design has sufficient margin to accommodate part-to-part and lot-to-lot variations; as well as, eliminating product performance uncertainty in production volume. Historically, design engineers have optimized their circuit performance via trial and error, at the expense of sig.
•這些環路電容器的無功阻抗（Xc）.
•逆變器放大器的跨導（gm）.
•是否存在限流電阻（Rs）.
•是否存在自動增益控制（AGC）或自動電平控制（ALC）; 與集成振蕩器電路配合使用.
這些因素共同設定了設計的邊界條件. 這種邊界條件,通常稱為安全系數（SF）,是確保產品設計具有足夠的余量以適應零件到零件和批次間差異的重要參數; 以及消除產品性能不確定性的產量. 從歷史上看,設計工程師通過試驗和錯誤優化了電路性能,但犧牲了信號.
Fig. 1: The oscillator block and the key components that influence the overall performance of the timing loop.

圖1：振蕩器模塊和影響定時環路整體性能的關鍵部件.
　　nificant investment in time. Further, to properly determine the oscillator loop dynamics, the most accurate determination is made by breaking the oscillator loop and conducting key measurements using specialized equipment such as a current probe.
　　及時投入.此外,為了正確地確定振蕩器環路動態,通過使用諸如電流探頭的專用設備斷開振蕩器環路并進行關鍵測量來進行最準確的確定.
　　Lastly, these measurements become increasingly sensitive if the timing loop is driven by a tuning-fork (32.768- kHz) crystal. These crystals are extremely sensitive to loading effects and to accurately determine the in-circuit behavior of these components, extreme care and accuracy is essential. For instance, Automotive, medical and consumer electronics solutions typically use tuning fork crystals for their real-time-clocking (RTC) needs. If the selected SOP has limited gain margin, there is a high probability that some percentage of these crystals will not properly start under adverse conditions, such as cold operating temperature (–40°C).
　　最后,如果定時環由音叉（32.768-kHz）晶體驅動,則這些測量變得越來越敏感.這些晶體對負載效應非常敏感,并且準確地確定這些元件的在線行為,極其謹慎和準確性至關重要.例如,汽車,醫療和消費電子解決方案通常使用音叉晶體來滿足其實時時鐘（RTC）需求.如果所選擇的SOP具有有限的增益裕度,則很可能這些晶體中的某些百分比在不利條件下（例如冷工作溫度（-40℃））不能正常啟動.
Another example would be a product designed to address the ZigBee related solutions, which typically has a hard boundary condition of ±40 ppm relative to the carrier, for proper operation. This ±40-ppm operational window actually needs to account for
　　另一個例子是設計用于解決ZigBee相關解決方案的產品,該解決方案通常具有相對于載波±40ppm的硬邊界條件,以實現正確操作.這個±40 ppm的操作窗口實際上需要考慮
• Quartz crystal set tolerance.
• Shift through reflow.
• Stability over temperature.
• Aging during product-life-cycle (such as 5 years).
• Frequency pushing and pulling.
If the oscillator loop is not optimized, most of the ±40 ppm can be potentially consumed by the set tolerance of the quartz crystal alone, thereby causing potential field failures.
•石英晶體設置公差.
•通過回流轉換.
•溫度穩定性.
•產品生命周期中的老化（例如5年）.
•頻率推拉.
如果振蕩器環路未經優化,則單獨使用石英晶體的設定公差可能會消耗大部分±40 ppm,從而導致潛在的現場故障.
　　These frequency domain failures could be primarily attributed to the oscillator frequency drifting over temperature or long-term aging, to the point that the oscillator loop is no longer within the allocated ±40-ppm operational window. Besides the issues related to oscillator-loop accuracy in the frequency domain, the oscillator-loop drive level must also be properly quantified to ensure acceptable product performance over temperature and time. For instance, a typical 24-MHz SMT quartz crystal has a drive level specification of 100 µW max. If the quartz crystal is consistently being driven at some multiple of this limit, such as 200 µW; it is possible that, over temperature or time, the oscillator circuit might start to resonate permanently or intermittently — at a spurious or overtone mode of the quartz crystal. Although relatively low on the checklist of design engineers, the Pierce oscillator driven by an external resonator — such as a quartz crystal — can present a significant challenge during a typical product launch. Characterizing the oscillator loop during the design phase should be a priority to mitigate the risk during product launch as well as field returns down the road.
　　這些頻域故障主要歸因于振蕩器頻率隨溫度漂移或長期老化,導致振蕩器環路不再在分配的±40 ppm操作窗口內.除了與頻域振蕩器環路精度相關的問題外,還必須對振蕩器環路驅動電平進行適當量化,以確保在整個溫度和時間內可接受的產品性能.例如,典型的24 MHz SMT石英晶體的驅動電平規格最大為100μW.如果石英晶體始終以該極限的某個倍數驅動,例如200μW;在溫度或時間上,振蕩器電路可能會開始永久或間歇地諧振 - 處于石英晶體的寄生或泛音模式.雖然設計工程師的清單相對較低,但是由外部諧振器（例如石英晶體）驅動的皮爾斯振蕩器在典型的產品發布期間可能是一個重大挑戰.在設計階段表征振蕩器回路應該是減少產品發布期間風險以及現場返回的優先事項.
　　The Pierce Analyzer System To overcome these challenges and provide an accurate assessment of the oscillator loop dynamics, Abracon’s Advanced Engineering Team has developed a proprietary Pierce Analyzer System (PAS), designed to analyze both the standalone crystal, as well as the performance of that particular crystal in the final circuit.
Key PAS features
• Circuit characterization; provides best possible match between Quartz Crystal, oscillator loop and associated components.
• Eliminates probability of oscillator startup issues related to inadequate design or marginal component performance.
• Eliminates production launch issues related to crystal oscillator based timing circuit.
• Solves for design margin uncertainty.
• Provides customer’s oscillator circuit overview in the form of a detailed report, which could be an ideal 3rd party assessment for the design 　　history file or PPAP documentation. This report encompasses both the stand-alone crystal performance, as well as in-circuit behavior outlining safety factor as a function of crystal’s ESR, etc.
　　皮爾斯分析儀系統為了克服這些挑戰并提供振蕩器回路動態的準確評估,Abracon的高級工程團隊開發了專有的皮爾斯分析儀系統（PAS）,旨在分析獨立晶體以及特定晶體的性能晶體在最后的電路中.
關鍵PAS功能
•電路特性;提供石英晶體,振蕩器環路和相關組件之間的最佳匹配.
•消除與設計不足或邊緣組件性能相關的振蕩器啟動問題的可能性.
•消除與基于晶體振蕩器的定時電路相關的生產啟動問題.
•解決設計邊際不確定性問題.
•以詳細報告的形式提供客戶的振蕩器電路概述,這可能是設計歷史文件或PPAP文檔的理想第三方評估.本報告既包括獨立的晶體性能,也包括作為晶體ESR等函數的安全系數的在線行為.

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